The commonly assigned U.S. Pat. No. 5,349,612, entitled "Digital Serializer and Time Delay Regulator," issued to Bin Guo and James J. Kubinec on Sep. 30, 1994 discloses inter alia a technique for programming the delay time of a novel delay line implementation. Referring to FIG. 1 herein, as described in that application, a programmable delay line 100 comprises two serially coupled sections 110 and 120 of delay elements. Each delay element in both sections is configured to have a common delay time (T.sub.d).
A fixed-stage delay section 110 comprises K delay elements 112-1, 112-2, to 112-K coupled in series. A variable-stage delay section 120 comprises M serially coupled delay elements 122-1, 122-2, to 122-M having outputs connected to inputs of a multiplexer 124. In response to a digital command code, the multiplexer 124 selects one of the outputs of the M delay elements 122-1 to 122-M. If the digital command code is set to select the output of the ith delay element (122-i) , then the total delay time of the programmable delay line (T.sub.tot) may be computed as follows:
where T.sub.mux is the delay time through the multiplexer 124, assuming that all the paths through the multiplexer 124 ##EQU1## have the same delay time. The total delay time of the programmable delay line 100 thus has a fixed delay component T.sub.k, equal to K(T.sub.d)+T.sub.mux, and a variable delay component i(T.sub.d).
While the programmable delay line disclosed in Guo and Kubinec is believed adequate in its implementation, there are aspects of that delay line that may be disadvantageous in other implementations. For example, the programmable delay line 100 employs a multiplexer 124, which consumes space on the semiconductor substrate. In addition, the assumption that the delay times of each path through the multiplexer 124 is the same may be false.
The programmable delay line 100 may have a large fixed delay Home component, making it difficult to achieve short delay times. Since the programmable delay line 100 uses delay elements 112 and 122 having a common delay period, the resolution of the programmable delay line 100 is limited to the common delay period. If the resolution is improved by coupling the programmable delay line 100 to another programmable delay line having delay elements with a shorter common delay period, then an additional area of the substrate is used up for a second multiplexer.